1. Field of the Invention The present invention relates to a shift register device in which a plurality of data hold circuits are connected in series with each data hold circuit having a series-connected set of flip-flop and latch circuits.
2. Description of the Related Art
Shift register devices in which a plurality of flip-flop circuits are connected in series have currently been widely used. In such a shift register device, serial input data can be shifted without any data loss as the flip-flop circuits of every odd places and those of every even places operate reversely in logic.
With the above-mentioned structure, racing could occur partly due to a possible skew of a clock signal. As an attempt to solve this problem, a shift register device in which a plurality of latch circuits are added, one to the output terminal of each of plural series-connected flip-flop circuits, has been proposed by Japanese Patent Laid-Open Publication No. Hei 6-5090. This conventional shift register device will now be described with reference to FIGS. 4 and 5 of the accompanying drawings of the present specification.
In the shift register device 1, as shown in FIG. 4, serial successive bit data are inputted from an input terminal 2 and transmitted to the right and outputted from an output terminal 3, and a plurality of data hold circuits 4 are arranged in series on a bit line communicating with the input and output terminals 2, 3. Each of the data hold circuits 4 consists of a flip-flop circuit 5 and a latch circuit 6 which are connected in series.
In the meantime, a clock signal is inputted to an input line 8 from an input terminal 7, the input line 8 being connected to the respective control terminals of the flip-flop and latch circuits 5, 6. The flip-flop and latch circuits 5, 6 operate in reverse logic in correspondence with the input clock signal between the data hold circuits 4 of every odd place and those of every even place.
Further, as shown in FIG. 5, the bit data outputted from the flip-flop circuit 5 of each (preceding) data hold circuit 4 in correspondence with the clock signal is held by the latch circuit 6, and the latch circuit 6 outputs this held bit data to the flip-flop circuit 5 of a succeeding data hold circuit 4.
Thus the bit data is temporarily held by every latch circuit 6 while it is shifted sequentially by the successive flip-flop circuits 5. Consequently, even when the input operation of the succeeding flip-flop circuit 5 is delayed with respect to the output operation of the preceding flip-flop circuit 5 resulting from a possible skew of the clock signal, this succeeding flip-flop circuit 5 can receive as an input the bit data held by the preceding latch circuit 6, which is associated with the preceding flip-flop 5. Namely, the so-called racing problem, in which the bit data input to the preceding flip-flop circuit 5 is prematurely provided to the succeeding flip-flop circuit 5 can be prevented in the absence of a possible skew of the clock signal between the flip-flop and latch circuits 5, 6.
Practically, however, in this known shift register device 1, such a skew is not considered at all and, therefore, racing cannot completely be prevented. In other words, as shown in FIG. 6, if the clock signal, e.g. SCK (4), to be inputted to the latch circuit 6 is delayed with respect to that to be inputted to the flip-flop circuit 5 in the preceding data hold circuit 4, e.g. SCK (1), the bit data outputted from the flip-flop circuit 5 would happen to be outputted to the succeeding data hold circuit 4 without being held by the latch circuit 6 associated with the preceding flip-flop circuit 5.
At that time, if the input operation of the preceding flip-flop circuit 5 is yet delayed with respect to the output operation of the preceding flip-flop circuit 5, the bit data outputted to the succeeding flip-flop circuit 5 without being held by the preceding latch circuit 6 would happen to be outputted to the next to the succeeding data holding circuit 4 without being held by the last-named flip-flop circuit 5.